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x86: Check all 0s/1s vectors with standard_sse_constant_p
commit 77473a27ba
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu Jun 26 06:08:51 2025 +0800
x86: Also handle all 1s float vector constant
replaces
(insn 29 28 30 5 (set (reg:V2SF 107)
(mem/u/c:V2SF (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64])) 2031 {*movv2sf_internal}
(expr_list:REG_EQUAL (const_vector:V2SF [
(const_double:SF -QNaN [-QNaN]) repeated x2
])
(nil)))
with
(insn 98 13 14 3 (set (reg:V8QI 112)
(const_vector:V8QI [
(const_int -1 [0xffffffffffffffff]) repeated x8
])) -1
(nil))
...
(insn 29 28 30 5 (set (reg:V2SF 107)
(subreg:V2SF (reg:V8QI 112) 0)) 2031 {*movv2sf_internal}
(expr_list:REG_EQUAL (const_vector:V2SF [
(const_double:SF -QNaN [-QNaN]) repeated x2
])
(nil)))
which leads to
pr121015.c: In function ‘render_result_from_bake_h’:
pr121015.c:34:1: error: unrecognizable insn:
34 | }
| ^
(insn 98 13 14 3 (set (reg:V8QI 112)
(const_vector:V8QI [
(const_int -1 [0xffffffffffffffff]) repeated x8
])) -1
(expr_list:REG_EQUIV (const_vector:V8QI [
(const_int -1 [0xffffffffffffffff]) repeated x8
])
(nil)))
during RTL pass: ira
Check all 0s/1s vectors with standard_sse_constant_p to avoid unsupported
all 1s vectors.
Co-Developed-by: H.J. Lu <hjl.tools@gmail.com>
gcc/
PR target/121015
* config/i386/i386-features.cc (ix86_broadcast_inner): Check all
0s/1s vectors with standard_sse_constant_p.
gcc/testsuite/
PR target/121015
* gcc.target/i386/pr121015.c: New test.
This commit is contained in:
@ -3534,22 +3534,20 @@ ix86_broadcast_inner (rtx op, machine_mode mode,
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machine_mode *scalar_mode_p,
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x86_cse_kind *kind_p, rtx_insn **insn_p)
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{
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if (op == const0_rtx || op == CONST0_RTX (mode))
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switch (standard_sse_constant_p (op, mode))
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{
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case 1:
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*scalar_mode_p = QImode;
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*kind_p = X86_CSE_CONST0_VECTOR;
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*insn_p = nullptr;
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return const0_rtx;
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}
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else if ((GET_MODE_CLASS (mode) == MODE_VECTOR_INT
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&& (op == constm1_rtx || op == CONSTM1_RTX (mode)))
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|| (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
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&& float_vector_all_ones_operand (op, mode)))
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{
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case 2:
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*scalar_mode_p = QImode;
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*kind_p = X86_CSE_CONSTM1_VECTOR;
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*insn_p = nullptr;
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return constm1_rtx;
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default:
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break;
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}
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mode = GET_MODE (op);
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32
gcc/testsuite/gcc.target/i386/pr121015.c
Normal file
32
gcc/testsuite/gcc.target/i386/pr121015.c
Normal file
@ -0,0 +1,32 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=x86-64-v3" } */
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extern union {
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int i;
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float f;
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} int_as_float_u;
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extern int render_result_from_bake_w;
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extern int render_result_from_bake_h_seed_pass;
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extern float *render_result_from_bake_h_primitive;
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extern float *render_result_from_bake_h_seed;
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float
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int_as_float(int i)
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{
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int_as_float_u.i = i;
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return int_as_float_u.f;
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}
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void
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render_result_from_bake_h(int tx)
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{
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while (render_result_from_bake_w) {
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for (; tx < render_result_from_bake_w; tx++)
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render_result_from_bake_h_primitive[1] =
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render_result_from_bake_h_primitive[2] = int_as_float(-1);
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if (render_result_from_bake_h_seed_pass) {
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*render_result_from_bake_h_seed = 0;
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}
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}
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}
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