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https://github.com/cirosantilli/linux-kernel-module-cheat.git
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799 lines
41 KiB
HTML
799 lines
41 KiB
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<meta name="description" content="The perfect emulation setup to study and develop the <<linux-kernel>> v5.9.2, kernel modules, <<qemu-buildroot-setup,QEMU>>, <<gem5-buildroot-setup,gem5>> and x86_64, ARMv7 and ARMv8 <<userland-assembly,userland>> and <<baremetal-setup,baremetal>> assembly, <<c,ANSI C>>, <<cpp,C++>> and <<posix,POSIX>>. EVERYTHING is built from source. <<gdb>> and <<kgdb>> just work. Powered by <<about-the-qemu-buildroot-setup,Buildroot>> and <<about-the-baremetal-setup,crosstool-NG>>. Highly automated. Thoroughly documented. Automated <<test-this-repo,tests>>. "Tested" in an Ubuntu 20.04 host.">
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<title>Linux Kernel Module Cheat</title>
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</head>
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<body id="msi-cache-coherence-protocol" class="article">
|
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<div id="header">
|
||
<h1>Linux Kernel Module Cheat</h1>
|
||
</div>
|
||
<div id="content">
|
||
<div class="sect4">
|
||
<h5 id="msi-cache-coherence-protocol"><a class="anchor" href="#msi-cache-coherence-protocol"></a><a class="link" href="#msi-cache-coherence-protocol">37.6.1.4. MSI cache coherence protocol</a></h5>
|
||
<div class="paragraph">
|
||
<p><a href="https://en.wikipedia.org/wiki/MSI_protocol" class="bare">https://en.wikipedia.org/wiki/MSI_protocol</a></p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This is the most basic non-trivial coherency protocol, and therefore the first one you should learn.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Compared to the <a href="vi-cache-coherence-protocol.html">VI cache coherence protocol</a>, MSI:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>adds one bit of knowledge per cache line (shared)</p>
|
||
</li>
|
||
<li>
|
||
<p>splits Valid into Modified and Shared depending on the shared bit</p>
|
||
</li>
|
||
<li>
|
||
<p>this allows us to not send BusUpgr messages on the bus when writing to Modified, since we now we know that the data is not present in any other cache!</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Helpful video: <a href="https://www.youtube.com/watch?v=gAUVAel-2Fg" class="bare">https://www.youtube.com/watch?v=gAUVAel-2Fg</a> "MSI Coherence - Georgia Tech - HPCA: Part 5" by Udacity.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Let’s focus on a single cache line representing a given memory address.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The system looks like this:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre>+----+
|
||
|DRAM|
|
||
+----+
|
||
^
|
||
|
|
||
v
|
||
+--------+
|
||
| BUS |
|
||
+--------+
|
||
^ ^
|
||
| |
|
||
v v
|
||
+------+ +------+
|
||
|CACHE1| |CACHE2|
|
||
+------+ +------+
|
||
^ ^
|
||
| |
|
||
| |
|
||
+----+ +----+
|
||
|CPU1| |CPU2|
|
||
+----+ +----+</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>MSI stands for which states each cache can be in for a given cache line. The states are:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>Modified: a single cache has the valid data and it has been modified from DRAM.</p>
|
||
<div class="paragraph">
|
||
<p>Both reads and writes are free, because we don’t have to worry about other processors.</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>Shared: the data is synchronized with DRAM, and may be present in multiple caches.</p>
|
||
<div class="paragraph">
|
||
<p>Reads are free, but writes need to do extra work.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This is the "most interesting" state of the protocol, as it allows for those free reads, even when multiple processors are using some address.</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>Invalid: the cache does not have the data, CPU reads and writes need to do extra work</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The above allowed states can be summarized in the following table:</p>
|
||
</div>
|
||
<div class="literalblock">
|
||
<div class="content">
|
||
<pre> CACHE1
|
||
MSI
|
||
M nny
|
||
CACHE2 S nyy
|
||
I yyy</pre>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The whole goal of the protocol is to maintain that state at all times, so that we can get those free reads when in shared state!</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>To do so, the caches have to pass messages between themselves! This means generating bus traffic, which has a cost and must be kept to a minimum.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>The system components can receive and send the following messages:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>CPUn can send to CACHEn:</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>"Local read": CPU reads from cache</p>
|
||
</li>
|
||
<li>
|
||
<p>"Local write": CPU writes to cache</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>CACHEn to itself:</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>"Evict": the cache is running out of space due to another request</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>CACHEn can send the following message to the bus.</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>"Bus read": the cache needs to get the data. The reply will contain the full data line. It can come either from another cache that has the data, or from DRAM if none do.</p>
|
||
</li>
|
||
<li>
|
||
<p>"Bus write": the cache wants to modify some data, and it does not have the line.</p>
|
||
<div class="paragraph">
|
||
<p>The reply must contain the full data line, because maybe the processor just wants to change one byte, but the line is much larger.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>That’s why this request can also be called "Read Exclusive", as it is basically a "Bus Read" + "Invalidate" in one</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>"Invalidate": the cache wants to modify some data, but it knows that all other caches are up to date, because it is in shared state.</p>
|
||
<div class="paragraph">
|
||
<p>Therefore, it does not need to fetch the data, which saves bus traffic compared to "Bus write" since the data itself does not need to be sent.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>This is also called a Bus Upgrade message or BusUpgr, as it informs others that the value is going to be upgraded.</p>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>"Write back": send the data on the bus and tell someone to pick it up: either DRAM or another cache</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>When a message is sent to the bus:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>all other caches and the DRAM will see it, this is called "snooping"</p>
|
||
</li>
|
||
<li>
|
||
<p>either caches or DRAM can reply if a reply is needed, but other caches get priority to reply earlier if they can, e.g. to serve a cache request from other caches rather than going all the way to DRAM</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>When a cache receives a message, it do one or both of:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>change to another MSI state</p>
|
||
</li>
|
||
<li>
|
||
<p>send a message to the bus</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>And finally, the transitions are:</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>Modified:</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>"Local read": don’t need to do anything because only the current cache holds the data</p>
|
||
</li>
|
||
<li>
|
||
<p>"Local write": don’t need to do anything because only the current cache holds the data</p>
|
||
</li>
|
||
<li>
|
||
<p>"Evict": have to save data to DRAM so that our local modifications won’t be lost</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>Move to: Invalid</p>
|
||
</li>
|
||
<li>
|
||
<p>Send message: "Write back"</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>"Bus read": another cache is trying to read the address which we owned exclusively.</p>
|
||
<div class="paragraph">
|
||
<p>Since we know what the latest data is, we can move to "Shared" rather than "Invalid" to possibly save time on future reads.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>But to do that, we need to write the data back to DRAM to maintain the shared state consistent. The <a href="mesi-cache-coherence-protocol.html">MESI cache coherence protocol</a> prevents that extra read in some cases.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>And it has to be either: before the other cache gets its data from DRAM, or better, the other cache can get its data from our write back itself just like the DRAM.</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>Move to: Shared</p>
|
||
</li>
|
||
<li>
|
||
<p>Send message: "Write back"</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>"Bus write": someone else will write to our address.</p>
|
||
<div class="paragraph">
|
||
<p>We don’t know what they will write, so the best bet is to move to invalid.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>Since the writer will become the new sole data owner, the writer can get the cache from us without going to DRAM at all! This is fine, because the writer will be the new sole owner of the line, so DRAM can remain dirty without problems.</p>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>TODO Wikipedia requires a Flush there, why? <a href="https://electronics.stackexchange.com/questions/484830/why-is-a-flush-needed-in-the-msi-cache-coherency-protocol-when-moving-from-modif" class="bare">https://electronics.stackexchange.com/questions/484830/why-is-a-flush-needed-in-the-msi-cache-coherency-protocol-when-moving-from-modif</a></p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>Move to: Invalid</p>
|
||
</li>
|
||
<li>
|
||
<p>Send message: "Write back"</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>Shared: TODO</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>"Local read":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Local write":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Evict":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Bus read":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Bus write":</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
<li>
|
||
<p>Invalid: TODO</p>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p>"Local read":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Local write":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Evict":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Bus read":</p>
|
||
</li>
|
||
<li>
|
||
<p>"Bus write":</p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
<div class="paragraph">
|
||
<p>TODO gem5 concrete example.</p>
|
||
</div>
|
||
<div class="ulist">
|
||
<ul>
|
||
<li>
|
||
<p><a href="msi-cache-coherence-protocol-with-transient-states.html">MSI cache coherence protocol with transient states</a></p>
|
||
</li>
|
||
</ul>
|
||
</div>
|
||
</div>
|
||
<div class="paragraph nav-footer">
|
||
<p>← Previous: <a href="vi-cache-coherence-protocol.html">VI cache coherence protocol</a> | ↑ Up: <a href="cache-coherence.html">Cache coherence</a> | ⌂ Home: <a href="README.html">Linux Kernel Module Cheat</a> | Next: <a href="msi-cache-coherence-protocol-with-transient-states.html">MSI cache coherence protocol with transient states</a> →</p>
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